Modify and Simulate

Once you've got the toolflow up and running on a beefy computer, you'll be ready to modify and simulate the Sparrow Albatros spectrometer design.

Modify the design

The Sparrow Albatros design is built using Simulink and the CASPER libraries. To modify the design:

  1. Launch MATLAB and navigate to your project directory
  2. Open the Simulink model file sparrow_albatros_spec.slx
  3. Make your desired changes to the design
  4. Add or modify blocks from the CASPER library
  5. Adjust parameters on existing blocks
  6. Create new subsystems for complex functionality
  7. Connect signals between blocks with appropriate data types

When modifying the design, keep these tips in mind:

  • Always maintain synchronization between signal paths
  • Check data bit widths at key points in your design
  • Consider timing implications when adding complex logic
  • Use the CASPER yellow blocks for hardware interfaces
  • Add test points at critical junctions to aid in simulation

Simulate the design

Simulation is a crucial step before synthesis and implementation. It allows you to verify the logical correctness of your design without the time-consuming FPGA build process.

To simulate your design:

  1. Configure simulation parameters:
  2. Click on the "Simulation" menu in Simulink
  3. Select "Model Configuration Parameters"

  4. Set appropriate stop time and solver options

  5. Add test signals:

  6. Use MATLAB Function blocks or From Workspace blocks to generate test vectors
  7. Configure step sources or sine wave generators for predictable input patterns

  8. Consider using recorded ADC data for realistic testing

  9. Add monitoring tools:

  10. Place Scope blocks to visualize signals during simulation
  11. Use To Workspace blocks to save simulation results for later analysis

  12. Add Display blocks to show numerical values at key points

  13. Run the simulation:

  14. Click the "Run" button in the Simulink toolbar
  15. Monitor signals in real-time on Scope blocks

  16. Adjust simulation speed as needed

  17. Analyze results:

  18. Verify that signals behave as expected at each processing stage
  19. Check for timing issues, overflows, or unexpected values
  20. Use MATLAB scripts to post-process simulation outputs

For example, to simulate the FFT behavior: - Create test signals with known frequency components - Run the simulation through the PFB and FFT stages - Visualize the output to confirm frequency bin mapping - Verify that the shift schedule prevents overflows

Synthesize and Implement the design

After successful simulation, proceed to build the FPGA design:

  1. Run the CASPER toolflow script with appropriate parameters
  2. Monitor the compilation process for warnings and errors
  3. Review resource utilization reports

During these stages, the design goes through three transformations: - Compilation (Simulink model → HDL) - Synthesis (HDL → logic gates) - Implementation (logic gates → hardware configuration)

Open up the synthesized design in Vivado and check timing

After synthesis, examine the timing reports in Vivado to ensure all timing constraints are met. Pay special attention to: - Clock domain crossings - Critical paths - Setup and hold time violations

For more details on these stages, see Gateware Compile, Synthesize, and Implement.